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PLL702-05
Low EMI Peripheral Clock Generator for Notebook
FEATURES
* * * * * * * Single Low EMI IC to replace multiple crystals and oscillators on Notebooks (27MHz, 14.318MHz, 24.576MHz, 25MHz). Selectable crystal input: 24.576MHz or 14.318MHz (accuracy requirement +/- 20ppm) Less than 10ppm Frequency Synthesis error, meeting AC97, IEEE1394, IEEE802 frequency precision specification. 27MHz clock with 2 levels of Selectable Spread Spectrum modulation +/- 0.5% and +/- 0.75% center. 25MHz clock with double drive strength (Ethernet PHY and MAC). 24.576MHz clocks for Audio Codec and IEEE1394. Available in 8-Pin SOIC.
PIN ASSIGNMENT
XIN XOUT VSS 24.576MHz/SST0* T
1 2 3 4
8 7 6 5
VDD 27_14.318MHz/XTAL_SEL* v VSS 25MHzx2
Note: 25MHzx2: double drive strength v: Internal pull-down resistor (120k)
POWER GROUPS
* VDD - VSS: XIN, XOUT, analog core, digital part , 27MHz., 24.576MHz and 25MHz.
PLL702-05
T:
*: Bi-directional pin Tri-level input
Table 1. SPREAD SPECTRUM SELECTION
SST0 1 0 M SST Modulation only on 27MHz. (pin 7) +/- 0.75 % +/- 0.5 % SST OFF (Default)
Table 2. CRYSTAL SELECTION TABLE
Crystal Input 24.576MHz 14.318MHz XTAL_SEL 0 1 Pin 7 27MHz 14.318MHz
Notes: M = Do not connect. 1 = Pulled up. 0 = Pulled down.
BLOCK DIAGRAM
XTAL_SEL SST(0) XIN XOUT
XTAL OSC
PLL SST
27_14.318MHz
24.576MHz
PLL2
25MHz
Note : Only 27MHz output is modulated for low EMI via Spread Spectrum.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 08/12/04 Page 1
PLL702-05
Low EMI Peripheral Clock Generator for Notebook
PIN DESCRIPTIONS
Name
XIN XOUT VSS 24.576MHz/SST0 25MHzx2
Pin#
1 2 3,6 4 5
Type
I O P B O
Description
Crystal input: accepts either 24.576MHz or 14.31818MHz fundamental crystal (CL = 20pF, parallel resonant mode, +/-20ppm). On-chip load capacitors: no external load capacitors required. (See the table #4 ) Crystal output. Ground connection. Bi-directional and Tri-Level pin. Upon power-on, the value of SST0 is latched in and used to select the SST control (see Spread Spectrum selection table 1). Tri level input: M = Do not connect, 1 = Pull up, 0 = Pull down. After power-up this pin acts as 24.576MHz output clock. 25MHz Ethernet output clock (double drive strength). Bi-directional pin. Upon power-on, the value of XTAL_SEL is latched in and used to set the input crystal frequency (24.575MHz or 14.31818MHz). Set XTAL_SEL to 0 (default) for 24.576MHz input crystal, set XTAL_SEL to 1 for 14.31818MHz input crystal (see Crystal Selection Table on page 1). . After power-up this pin acts as 27MHz output (with 24.576MHz crystal) or as 14.31818MHz pass through clock (with 14.31818MHz crystal), depending on the input crystal. The 27MHz output can be modulated for low EMI using Spread Spectrum. 3.3V power supply for 27MHz, oscillator, analog core and digital circuitry.
27_14.318MHz/XTAL_SEL
7
B
VDD
8
P
FUNCTIONAL DESCRIPTION Tri-level and two-level inputs
In order to reduce pin usage, the PLL702-05 uses tri-level input pins. These pins allow 3 levels for input selection: namely, 0 = Connect to GND, 1 = Connect to VDD, M = Do not connect. Thus, unlike the two-level selection pins, the tri-level input pins are in the "M" (mid) state when not connected. In order to connect a tri-level pin to a logical "zero", the pin must be connected to GND. Likewise, in order to connect to a logical "one", the pin must be connected to VDD.
Connecting a bi-directional pin
The PLL702-05 also uses bi-directional pins. The same pin serves as input upon power-up, and as output as soon as the inputs have been latched. The value of the input is latched-in upon power-up. Depending on the pin (see pin description), the input can be tri-level or a standard two-level. Unlike unidirectional pins, bi-directional pins cannot be connected directly to GND or VDD in order to set the input to "0" or "1", since the pin also needs to serve as output. In the case of two level input pins, an internal pullup resistor is present. This allows a default value to be set when no external pull down resistor is connected between the pin and GND (by definition, a tri-level input has a the default value of "M" (mid) if it is not connected). In order to connect a bidirectional pin to a non-default value, the input must be connected to GND or VDD through an external pull-down/pull-up resistor. Note: when the output load presents a low impedance in comparison to the internal pull-up resistor, the internal pull-up resistor may not be sufficient to pull the input up to a logical "one", and an external pull-up resistor may be required. For bi-directional inputs, the external loading resistor between the pin and GND has to be sufficiently small (compared to the internal pull-up resistor) so that the pin voltage be pulled below 0.8V (logical "zero"). In order to avoid loading effects when the pin serves as output, the value of the external pull-down resistor should however be kept as large as possible. In general, it is
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 08/12/04 Page 2
PLL702-05
Low EMI Peripheral Clock Generator for Notebook
recommended to use an external resistor of around one sixth to one quarter of the internal pull-up resistor (see Application Diagram). Note: when the output is used to drive a load presenting an small resistance between the output pin and VDD, this resistance is in essence connected in parallel to the internal pull-up resistor. In such a case, the external pull-down resistor may have to be dimensioned smaller to guarantee that the pin voltage will be low enough achieve the desired logical "zero". This is particularly true when driving 74FXX TTL components.
APPLICATION DIAGRAM: BI-DIRECTIONAL PINS WITH INTERNAL PULL-DOWN
Vcc
Jumper options
Bi-directional pin Output
EN
Clock Load
Tri-Level pin Power Up Reset
R RB
RDOWN/4 Rdown
Jumper options
Latched Input
Latch Internal to chip External Circuitry
NOTE: Rdn=Internal pull-down resistor (see pin description). Power-up Reset : R starts from 1 to 0 while RB starts from 0 to 1.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 08/12/04 Page 3
PLL702-05
Low EMI Peripheral Clock Generator for Notebook
Electrical Specifications
1. Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model
SYMBOL
VDD VI VO TS TA TJ
MIN.
-0.5 -0.5 -65 -40
MAX.
4.6 VDD+0.5 VDD+0.5 150 85 125 260 2
UNITS
V V V C C C C kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. AC Specifications PARAMETERS
Input Frequency (to be set via XTAL_SEL) Output Rise Time Output Fall Time Duty Cycle Max. Absolute Period Jitter Max. Jitter, cycle to cycle Clock Settle Time Crystal Load Capacitance Crystal ESR Excluding PCB parasitics
CONDITIONS
+/- 20ppm accuracy 10% to 90% with no load 90% to 10% with no load At VDD/2 Long term, No SST Long term + Short term
MIN.
TYP.
14.31818 24.576
MAX.
UNITS
MHz MHz
0.5 0.5 40 50 60 500 400 22 21 30 25
ns ns % ps ps ms pF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 08/12/04 Page 4
PLL702-05
Low EMI Peripheral Clock Generator for Notebook
3. DC Specifications PARAMETERS
Operating Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output High Voltage At CMOS Level Nominal Output Current Operating Supply Current Short-circuit Current
SYMBOL
VDD VIH VIL VIH VIL VIH VIL VOH VOL VOH IOUT IDD IS
CONDITIONS
Nominal voltage 3.3V
MIN.
2.97
TYP.
VDD/2 VDD/2
MAX.
3.63 VDD/2 - 1 0.5
UNITS
V V V V V V V V
For all Tri-level input For all Tri-level input For all normal input For all normal input IOH = -10mA (normal drive) IOH = -20mA (double drive) IOL = 10mA (normal drive) IOL = -20mA (double drive) IOH = -8mA Normal drive strength Double drive strength No Load
VDD-0.5 2 0.8 2.4 0.4 VDD-0.4 10 20 23 100
V V mA mA mA
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 08/12/04 Page 5
PLL702-05
Low EMI Peripheral Clock Generator for Notebook
PACKAGE INFORMATION
8 PIN Narrow SOIC ( mm )
SOIC Symbol A A1 B C D E H L e Min. 1.55 0.10 0.33 0.19 4.80 3.81 5.08 0.41 1.27 BSC Max. 1.73 0.25 0.48 0.25 4.98 3.99 6.20 0.89 E H
D
A 1 e B
A C L
ORDERING INFORMATION
For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following: Device number, Package type and Operating temperature range
PLL702-05 S C
PART NUMBER TEMPERATURE C=COMMERCIAL
PACKAGE TYPE S = SOIC
Order Number PLL702-05SC-R PLL702-05SC
Marking P702-05SC P702-05SC
Package Option SOIC -Tape and Reel SOIC -Tube
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 08/12/04 Page 6

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